Erratum
In the original published version of this article [1], the third co-author’s name Kothari Dwarkadas Pralhaddas appears twice, and the name of the second co-author Alagan Anpalagan is missing. The correct author list is as follows:
Vijayalakshmi Saravanan, Alagan Anpalagan, Kothari Dwarkadas Pralhaddas and Isaac Woungang
The publisher apologies for this error introduced during publication of this article.
Reference
Saravanan V, Pralhaddas KD, Kothari DP, Woungang I (2015) An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs. Human-Centric Comput Inf Sci 5:2
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The online version of the original article can be found under doi:10.1186/s13673-014-0016-8.
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Saravanan, V., Anpalagan, A., Pralhaddas, K.D. et al. Erratum to: An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs. Hum. Cent. Comput. Inf. Sci. 5, 9 (2015). https://doi.org/10.1186/s13673-015-0026-1
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DOI: https://doi.org/10.1186/s13673-015-0026-1