Within the FACETS research project, a neuromorphic mixed-signal VLSI device was created . It was designed to exhibit a linear correspondence with an I&F neuron model, including synaptic plasticity and short-term synaptic dynamics. It operates with a speedup factor of around 105 compared to biological real time. Utilizing the existing prototype, networks of up to 384 neurons and the temporal evolution of the weights of 105 synapses under STDP can be modeled.
We developed a software framework which allows a unified access to both the hardware system and the pure software neuro-simulator NEST, providing the possibility to verify that the chip can be operated in a biologically realistic regime. From within a single software scope, we can compare and post-process results obtained from both systems, based on identical input and network setups.
We present experiments that illustrate the status of hardware neuron model verification by comparing its dynamics to NEST simulations. Exemplarily, Figure 1 shows the linear correspondence between the hardware and the software neuron model.
Figure 1. The membrane potentials of a single neuron under Poisson process input. The upper one has been simulated using NEST, the lower one is a digitization of the analog voltage trace of the neuromorphic hardware.
To establish neuromorphic hardware as a valuable tool for neuroscience, its biological correctness has to be proven. We provide a tool for the direct comparison of a specific hardware system and a simulation software. Our experimental data illustrates the functionality of the hardware and shows its biological relevance. The resulting uniform software interface will allow modelers to port existing network models to the hardware system with minimal effort.
This work is supported by the European Union under the grant no. IST-2005-15879 (FACETS).