Methodology article

Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

Yoginder S Dandass^{* 1,2} , Shane C Burgess^1,3,4 , Mark Lawrence^1,4 and Susan M Bridges^{* 1,2}

¹Institute of Digital Biology, Mississippi State University, Mississippi, 39762, USA

²Department of Computer Science and Engineering, Mississippi State University, Mississippi, 39762, USA

³Life Science and Biotechnology Institute, College of Veterinary Medicine, Mississippi State University, Mississippi, 39762, USA

⁴Department of Basics Science, Mississippi State University, Mississippi, 39762, USA

author email corresponding author email* Contributed equally

BMC Bioinformatics 2008, 9:197doi:10.1186/1471-2105-9-197

Published:	15 April 2008

Abstract

Background

This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA) devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM) is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences).

Results

This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM) resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs.

Conclusion

Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.